In the Fall 2011 semester, I was enrolled in a class named ECE 437: Computer Design and Prototyping (aka Computer Architecture). The semester-long project in that class was a MIPS-based microprocessor. As the semester progressed, my partner and I evolved our design to become more and more complex. We individually started with a single-cycle CPU, then teamed up for pipelining, caching, and turning it into a dual-core processor.
Since I loved the class and the project, I decided to stay after finals and fix a few bugs that bothered me and implement memory-mapped I/O. I then made a demonstration video so I could show my friends and family what I had been doing with my education.
These are the features that are implemented in my processor. The links are for those that are not quite up-to-date on their computer architecture.
- Implements a sub-set of the MIPS ISA
- 32 32-bit registers
- 5-stage pipeline
- Predict-not-taken branching
- Full forwarding to the instruction decode and execute stages
- 16-word, direct mapped instruction cache (per core)
- 64-word, two-way set associative, write back data cache (per core)
- Fully-implemented the MSI protocol to maintain coherence
- MIPS Load-linked/Store-conditional support
- Cache-to-cache transfer using a snoopy bus
- LED, 7-segment, and 16×2 character LCD memory-mapped outputs
- DIP switch and push button memory-mapped inputs
- 1 μSec timer peripheral (memory-mapped as well)
- 26.3 – 28.6ns critical path (35 – 38 MHz)
- About 20k FPGA logic block (~57% of the Cyclone II FPGA used to test)
Here is the video I created of a couple demonstration programs. The first program I demonstrate is a four-function calculator, which is a single-core program focused on showing off the I/O and general performance. The second program is a merge/insertion sort program designed to compare the performance of using two cores rather than just a single one. Enjoy!
If you aren’t satisfied with the detail on this page, I applaud your curiosity. If you care to learn more, you can read my final report (PDF, 4.8 MB, sorry) for the class, which includes more details as well as project analysis and schematics. This report includes details of the processor at the end of the school semester, before I fixed some timing bugs that were limiting our clock speed and implemented memory-mapped I/O.
If you have any more questions about the processor, feel free to email me at .