Digital Oscilloscope ASIC Project

In the spring semester of 2011, I took my first class dealing with designing digital hardware at the chip level. That class was titled “ASIC Design Laboratory” and I instantly fell in love with the material.

The first half of the semester I learned the basics of VHDL: syntax, shift registers, RTL, etc. Some of the “small” lab projects included designing a UART receiver and a USB receiver.

For the second half of the semester, I joined two other students and we started our semester project. The assignment was to create an ASIC chip that did something that could not be done in a microcontroller, with special emphasis on power usage and speed. We decided to create an oscilloscope-on-a-chip designed with students in mind. It was designed to input two channels of analog data (passed through an off-chip A/D),  perform common oscilloscope functions (time/magnitude division, cursors, triggering, etc.), and output the results to a DVI interface.

Block Diagram

This first diagram is the block diagram of the entire product. It is divided into the inputs and outputs from the “outside world”, the components on the PCB, and the chip itself. One note: though I now understand them, at the time, I did not really understand how LVDS signals worked, so the DVI interface is incorrect.

Diagram 1 - Product Block Diagram

This second diagram is the block diagram of the internals of the chip that we designed. Not pictured is the internal SRAM that the Graphics Controller interfaced with. We divided up the three major blocks between the three team members. I worked on the Sample Processor and the Button Register. As the project neared completion, more help was needed on the Graphics Controller, so I also helped a bit with that block.

Diagram 2 - Internal Block Diagram

 Test Bench Outputs

I designed the overall test bench for our product. It used text files as signal/button inputs and output a text file describing the pixels output by the chip. A simple MATLAB script was created to write the input files and convert the output into a PNG image. Below are some of the sample output files (cropped to eliminate extra blank space).

Figure 1 - Time division by four, channel 1 (blue) voltage divided by two, triggered on channel 2 (at zero, rising)

Figure 2 - Same as Figure 1, but with the time division set at eight and the trigger is 112, rising on channel 2 (green). The phase offset of two is probably due to the averaging inside the Input Processor.

Figure 3 - Cursor and ohase offset test (see figure 4 for a closer view). The cursors are at sample 190 and 210 (the maximum and minimum of each wave).

Figure 4 - A zoomed-in view of a peak to show the correct phase offset calculation.

 Layout

Using Synopsys SoC Encounter, we generated a layout for our chip. It is seen in Figure 5 below. The final chip area was 4.7 mm2 (not counting the 0.4 mm2 needed for the on-chip SRAM, which was not available for layout). The layout was not perfect, and since the compilation took about two hours each time, we unfortunately ran out of time before our final presentation.

Figure 5 - The layout of our chip.

 Project Analysis

Since this was our first “large” digital hardware design project, it was a really a rocky experience throughout. Of course overcoming those obstacles made me much more aware of the kind of things that need to be done to complete a successful digital hardware design project.

We had some pretty severe timing issues in the graphics controller that we could not fix. These are due to having to drive a 640×480 display fast enough to satisfy DVI requirements. To make our goal more realistic, we had to cut a few features in the graphics controller. Instead of outputting DVI, we decided just to output three bits of graphics data (RGB) and a clock. I believe we could have gotten it to work if we had know about pipelining, but that was not taught in the class.